Abdellah Touhafi

Reconfigurable Measurement Systems

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What is?

EPP
Enhanced Parallel Port Protocol.  This protocol extends the parallel port with the ability to send and receive data at a rate of more than 1 Mbyte/s.

Meschan

Meschan is a reconfigurable measuring system that is configured as a low cost device for accurate inter-pulse distance measurement. The measurement accuracy is 50 ns in this revision (rev 1.0). The whole system is a set of two devices being a Front End and a backend which can be connected to any computer that supports an EPP compliant parallel port. The Front End is used to make sure that the sensing device which is connected to the measurement system is not loaded highly to conserve a great part of the original sensor-signal power. The output of the Front End is a TTL compliant signal with only limited noise. The inter-pulse distance measurement itself is done by the backend which contains a field programmable gate array (FPGA). The FPGA can be configured and reconfigured on field by using a Xilinx serial download cable. This is a powerful option useful when experimental changes must be made. In normal working mode the default configuration is downloaded from an EPROM. The Back End contains also two indication LEDís, four BNC input connectors, four jumpers for the mode setting and one parallel port connector.

Hardware Specifications and description:

The Front End: The front end is based on the NE527 voltage comparator. The technical specifications of that component can be found in the appendix. This front end is basically a Schmidt trigger with a very high impedant input (more than 10 MOhm) and a very low output impedance (a few ohm). The threshold voltage can be changed by a potentio-meter and the hysteresis has a fixed value of Ė10mv to +10 mV. The result is a very clean TTL compliant output signal. The minimal input pulse-width is limited to a minimum of 50 ns due to the introduced jitter in the output signal for lower pulse-widths.

The Back End: The central component of the backend (BE) is the XC4010 FPGA of Xilinx. The technical specifications of that component can be found in the appendix.

A choice out of two operation modes can be made by the right jumper settings. When the jumpers (M0 M1 M2 D/P1) are set as follows (0,0,1,1 where a zero means close and a one means open connection) the BE will operate in its normal working mode. This means that the device will automatically load itís configuration from an 8 bit wide EPROM. In this mode the FPGA becomes configured as an accurate pulse distance measurement system.

When the jumpers M0 M1 M2 D/P1 are set as ( 1,1,0,1) then the BE is set in itís program mode and can be configured on field with a configuration bit stream. This is possible since the BE contains an interface for the Xilinx download cable. The configuration bitstream can be generated using the Xilinx XACT step tools or any other tool which is Xilinx compliant. Downloading the generated bitstream can be done by Connecting the download cable to the system. This is a very practical option when changes must be made to the BE but this also means that the BE can be used for many other measurement applications.

The Backend provides also two indication LEDís. This LEDís are connected to pins 11 (LED2) and 12 (LED1) of the FPGA. The operation of the LEDís can be changed depending on the configuration of the system. In the current configuration they are used as operation visualizers: LED1 will light on ones the system is correctly configured while LED2 lights on during a measuring cycle. This is as long as the trigger signal is active (see FIRMWARE: measuring principle for more details on the trigger signal).

There are also 4 BNC connectors on the BE. This BNC connectors are terminated with a 50 Ohm resistance. There are also two unused positions on which any convenient BNC connector can be connected. In the current configuration two of the four BNC connectors are used as inputs. The BNC connector IN5 is used as input for the trigger signal and IN6 is used as input for the pulse signal.

The last component found on the BE is the Parallel port connector. This parallel port connector is connected such that all necessary signals for EPP mode can be used by the

FPGA. In the current configuration an EPP interface is implemented in the FPGA. More details about the EPP mode can be found in the appendix.

Firmware specifications and description :

Measuring principle: In this part we will describe how the internals of the XC4010 are programmed to make it suitable for the measurement of the time between two pulses. The measurement system contains three parts: the measuring part, a 16 byte FIFO memory that works with a maximal throughput of 40 Mb and an interfacing part for the EPP compliant parallel port. There is also some logic foreseen to do some internal tests to make sure that the system is connected correctly to the parallel port.

The measuring part is based on a 20 MHz clock and a 32 bit time-counter. The time-counter is reset as long as the trigger signal is not active (low). Ones the trigger becomes active the counter starts counting until the trigger becomes inactive. The smallest time between two pulses that can be measured is 50 ns and the maximum time between two pulses is 214 seconds. If the distance between two pulses is smaller than 50 ns it will be detected but the time is automatically set to 50 ns. When the distance between two pulses is greater than 214 seconds an overflow occurs and the measured time will be incorrect.

The FIFO memory is 16 bytes deep and is able to store four measurements. The functionality of the FIFO is to make sure that four measurements can be done with a small inter-pulse time. The problem exists that measurements could be lost due to a limited bandwidth of the parallel port. Measurements have shown that the bandwidth of the parallel port is about 100.000 measurements per second. This is in the case that the pulse train is continuously fast. The sensor delivers an average number of pulses which is about 10.000 per second but since the pulses are Poisson distributed there is a certain probability that two or more following pulses are very close to each other while other parts of the pulse-train can be lowfrequent.

The EPP interface is a fast bi-directional parallel port protocol. Since this application is a bandwidth demanding application and an external platform independent measuring device is preferable, the best solution is to use the parallel port. Also the most modern computers (PCís and workstations) provide an EPP interface standard on their motherboard. The throughput of the EPP parallel port varies between 1 Mbyte/s to more than 1.8 Mbyte/s. We have tested Meschan on a Pentium PC with an EPP parallel port with a throughput of 1 Mbyte/s. This resulted in a correct measurement of a maximum constant pulse rate of 100.000 pulses per second. The reason that the maximum pulse rate is lower than the maximum throughput is that some synchronization data has to be sent to make sure that the measurement is done correctly.